Power Analysis of CMOS Combinational Logic Circuits Using Adiabatic Reduction Technique at 180nm Technology

In recent years the adiabatic techniques have been used to reduce power consumption in various high end processors. Various adiabatic logic circuits have been proposed based on the energy recovery principle. The term “adiabatic” is derived from a reversible thermodynamic process and it stands for a system where a transformation takes place in such a way that no gain or loss of heat or energy occurs. This paper discusses an energy efficient way of designing the combinational logic circuits using adiabatic technique to minimise the power consumption. A comparative analysis for power consumption between conventional CMOS designs of the AND, NAND, OR, Inverter Logic and their adiabatic designs has been performed at 180nm. A power saving of up to 33% in AND gate, 16% in NAND, 6% in NOR and 5% in Inverter respectively is observed at VDD=1.8V, and T=27 0 C.